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RT5028C ? ds5028c-00 march 2015 www.richtek.com 1 ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pmic for industrial application general description the RT5028C is a highly-integrated low-power high- performance analog soc with pmic in one single chip designed for industrial applications. the RT5028C includes four synchronous step-down dc/ dc converters and eight ldos for system power. the RT5028C also embeds one eeprom (mtp) for setting sequence and timing etc. additionally, the RT5028C pmic also includes one irq report. simplified application circuit features ? ? ? ? ? input voltage operating range is 3.3v to 5.5v ? ? ? ? ? step-down regulator : v in range is 3.3v to 5.5v ? ? ? ? ? max current 2.4a/2a/1.6a/2a ? ? ? ? ? programmable frequency from 500khz to 2mhz ? ? ? ? ? i 2 c programmable output level ? ? ? ? ? i 2 c programmable operation mode (force pwm or auto psm/pwm) ? ? ? ? ? i 2 c programmable output discharge mode (discharge or flatting) ? ? ? ? ? linear regulators : v in range is 2.5v to 5.5v ? ? ? ? ? max current 0.3a ? ? ? ? ? i 2 c programmable output level ? ? ? ? ? embedded 32bytes mtp for factory tuning ? ? ? ? ? external mtp pin for write protection ? ? ? ? ? sequence can be controlled by i 2 c or each en pins defined by mask_gpio pin. ? ? ? ? ? ot/uvp/vin lv/powron press time interrupt (irq). ? ? ? ? ? i 2 c control interface: support fast mode up to 400kb/s ? ? ? ? ? rohs compliant and halogen free ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. applications ? industrial package type qw : wqfn-56l 7x7 (w-type) RT5028C lead plating system g : green (halogen free and pb free) RT5028C vinl456 vinl123 agnd vinl78 voutlx vddp vin vinbx lxbx voutbxs scl sda irq pwrhold pwron reboot mtp mask_gpio saddr reset enbx enlx
2 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 voutl1 output voltage regulation node for ldo1. 2 vinl123 input power for ldo1, ldo2 and ldo3. 3 voutl2 output voltage regulation node for ldo2. 4 voutl3 output voltage regulation node for ldo3. 5 voutl6 output voltage regulation node for ldo6. 6 voutl5 output voltage regulation node for ldo5. 7 vinl456 input power for ldo4, ldo5 and ldo6. 8 voutl4 output voltage regulation node for ldo4. 9 voutl7 output voltage regulation node for ldo7. 10 vinl78 input power for ldo7 and ldo8. 11 voutl8 output voltage regulation node for ldo8. 12 enl4 enable control input for ldo4. connect a 100k ? pull-low resistor. 13 enl5 enable control input for ldo5. connect a 100k ? pull-low resistor. 14 enl6 enable control input for ldo6. connect a 100k ? pull-low resistor. 15 scl clock input for i 2 c. open-drain output, connect a 10k ? pull-up resistor. pin configurations (top view) wqfn-56l 7x7 marking information RT5028Cgqw : product number ymdnn : date code voutl1 voutl3 voutl2 enl4 voutl8 vinl78 voutl7 voutl4 vinl456 voutl6 voutl5 vinl123 scl sda enl7 enl8 irq pwrhold agnd pwron reboot mtp mask_gpio lxb2 voutb2s enb2 vinb4 voutb3s agnd lxb3 lxb3 vinb3 vinb3 lxb2 enl3 enl2 enl1 vin vddp vinb1 voutb1s enb1 lxb1 lxb1 1 2 3 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 17 16 15 42 41 40 39 38 37 36 35 34 33 32 45 46 47 48 49 50 51 52 53 54 55 56 lxb4 31 enb3 30 voutb4s 29 saddr 27 enb4 28 enl5 13 enl6 14 vinb2 44 vinb2 43 agnd vinb1 agnd 57 reset RT5028C gqw ymdnn
3 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function 16 sda data input for i 2 c. open-drain output, connect a 10k ? pull-up resistor. 17 enl7 enable control input for ldo7. connect a 100k ? pull-low resistor. 18 enl8 enable control input for ldo8. connect a 100k ? pull-low resistor. 19 irq open-drain irq output node. 20 reset reset output. 21, 34, 56, 57 (exposed pad) agnd analog ground. the exposed pad must be soldered to a large pcb and connected to agnd for maximum power dissipation. 22 pwron manual power on. connect a 100k ? pull-up resistor. 23 reboot system power reboot. connect a 100k ? pull-low resistor. 24 mtp mtp write protection pin. connect a 100k ? pull-low resistor, logic low is inhibited and logic high is permit to write. 25 mask_gpio select i 2 c or use en pin for bucks and ldos. connect a 100k ? pull-low resistor. as mask_gpio is high, ignore all en pins. as mask_gpio is low, en pins and i 2 c both can control. en pins priority is higher than i 2 c. 26 pwrhold power hold input. connect a 100k ? pull-low resistor. 27 saddr i 2 c slave address. connect a 100k ? pull-low resistor. 28 enb4 enable control input for buck4. connect a 100k ? pull-low resistor. 29 voutb4s output voltage regulation node for buck4. 30 enb3 enable control input for buck3. connect a 100k ? pull-low resistor. 31 lxb4 internal switch node to output inductor connection for buck4. 32 vinb4 input power for buck4. 33 voutb3s output voltage regulation node for buck3. 35, 36 lxb3 internal switch node to output inductor connection for buck3. 37, 38 vinb3 input power for buck3. 39 voutb2s output voltage regulation node for buck2. 40 enb2 enable control input for buck2. connect a 100k ? pull-low resistor. 41, 42 lxb2 internal switch node to output inductor connection for buck2. 43, 44 vinb2 input power for buck2. 45, 46 vinb1 input power for buck1. 47, 48 lxb1 internal switch node to output inductor connection for buck1. 49 enb1 enable control input for buck1. connect a 100k ? pull-low resistor. 50 voutb1s output voltage regulation node for buck1 51 vddp internal bias regulator voltage. external load on this pin is not allowed. 52 vin input power for analog base. 53 enl1 enable control input for ldo1. connect a 100k ? pull-low resistor. 54 enl2 enable control input for ldo2. connect a 100k ? pull-low resistor. 55 enl3 enable control input for ldo3. connect a 100k ? pull-low resistor.
4 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram central controller i 2 c programmable state machine ldo1 300ma ldo2 300ma ldo3 300ma ldo4 300ma ldo5 300ma ldo6 300ma ldo7 300ma ldo8 300ma buck2 2a buck1 2.4a vinl123 vinl456 voutl2 voutl3 voutl4 voutl5 voutl6 voutl7 voutl8 sda scl irq pwrhold reboot vinb1 lxb1 voutb2s lxb2 vinb2 voutb1s mask_gpio saddr pwron enb1 to enb4 enl1 to enl8 mtp voutl1 vinl78 reset buck3 1.6a vinb3 lxb3 voutb3s buck4 2a vinb4 lxb4 voutb4s analog base vin vddp agnd gnd gnd gnd gnd
5 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the RT5028C is a highly-integrated solution for industrial system including 4-ch step-down dc/dc converters and 8-ch ldos. the RT5028C application mechanism will be introduced in later sections. the power-on and power-off sequences can be controlled by i 2 c or each en pin and detected in mask_gpio pin. when the mask_gpio pin is at hi level, the pmic follows the power-on sequence to turn on channels. when the mask_gpio pin is at lo level, the channels of pmic will be controlled by the en pin. synchronous step-down dc/dc converter four current mode synchronous step-down dc/dc converters operate with internal power mosfets, fb resistors and compensation network. these channels are suitable for core power in industrial system. they can be operated at 100% maximum duty cycle to extend battery operating voltage range. when the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. the operating frequency of step-down converter is adjustable from 500khz to 2mhz and is controlled by i 2 c. besides, the i 2 c interface also can be used to select different operation modes, on/off sequence, programmable the output voltage, ramp control and discharge function. to enable auto mode, it is used to improve the efficiency at light load. if the auto mode is disabled, the converter operates in force pwm mode with fixed switching frequency. linear regulator eight generic low voltage ldos for multiple purpose power. the ldos are stable over the entire operating load range with the use of external ceramic capacitors. the ldos also have i 2 c programmable power on/off sequence and discharge function. the output voltage is adjustable by the i 2 c interface in the range of 1.6v to 3.6v. over-temperature protection an over-temperature protection (otp) is contained in the device. the protection is triggered to force the device shutdown for protecting itself when the junction temperature exceeds 165 c typically. once the junction temperature drops below the hysteresis 10 c typically, the device must be re-send pwron to start system. output under-voltage protection the output under-voltage protection is implemented in order to prevent operation at low output voltage conditions. when the step-down dc/dc converters output voltage is lower than 1/2 x (v out ), the uvp event triggers and pmic turns off immediately.
6 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) ? analog base in put voltage, vin ---------------------------------------------------------------------------------------- ? 0.3v to 6v ? pmic input v oltage, vinl123/456/78, vinb1/2/3/4 ---------------------------------------------------------------- ? 0.3v to 6v ? pmic output voltage, voutlx, voutbxs, lxbx ----------------------------------------------------------------- ? 0.3v to 6v ? pmic related other pins -------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c wqfn-56l 7x7 ------------------------------------------------------------------------------------------------------------- 3.7w ? package thermal resistance (note 2) wqfn-56l 7x7, ja -------------------------------------------------------------------------------------------------------- 27 c/w wqfn-56l 7x7, jc ------------------------------------------------------------------------------------------------------- 7 c/w ? junction temperature ------------------------------------------------------------------------------------------------------ 150 c ? lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c ? storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ------------------------------------------------------------------------------------------------------ 200v recommended operating conditions (note 4) ? junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics (vin = 3.3v to 5.5v, t a = ? 40 c to 85 c, unless otherwise specified) parameter symbol test conditions min typ max unit operation voltage of vin as f sw > 1mhz, 3.3v ? v in ? 5.5v. if f sw ? 1mhz, v in ? 4v. 3.3 -- 5.5 v pmic v in = 5v, ldos, bucks are on with no load. 300 450 600 ? a quiescent current i in v in = 5v, ldos, bucks are off. scl = sda = 0v 5 20 40 ? a temperature 1 -- 100 -- warning for die temperature otw temperature 2 -- 125 -- ? c over-temperature protection otp -- 165 -- ? c otp and warning hysteresis -- 10 -- ? c input pull-low 100k resistor r low v in = 5v, temperature = ? 40 ? c to 125 ? c 70 115 160 k ?
7 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit buck1 to buck4 input voltage v inb 3.3 -- 5.5 v output voltage v outb buck1 i 2 c programmable per step 25mv 0.7 -- 1.8 v buck2 i 2 c programmable per step 25mv 0.7 -- 1.8 buck3 i 2 c programmable per step 50mv 0.7 -- 3.6 buck4 i 2 c programmable per step 50mv 0.7 -- 3.6 consum ption current i vinb auto mode i out = 0ma, each buck 10 20 40 ? a efficiency peak eff v out = 1.2v, v in = 3.6v i load = ccm -- 88 -- % i load = 1ma -- 80 -- output voltage accuracy v outacc 3.1v < v in < 5.5v, 1ma < i out < i max as voutb1s to voutb4s ? 1v. ? 3 -- 3 %mv as voutb1s to voutb4s < 1v. 30 -- 30 output voltage ripple v rip i out = 1ma, c out = 10 ? f, 2mhz -- 25 -- mv i out = 1a, c out = 10 ? f, 2mhz -- 8 -- output voltage temperature coefficien t -- 100 -- ppm/ ? c switching frequency f sw i 2 c programmable 0.43 -- 2 mhz switching frequency accuracy 1mhz ? f sw ? 10 -- 10 % f sw ? 1mhz ? 20 -- 20 suggest inductor l buck -- 2.2 -- ? h peak current limit ocp buck1 3.1 4.4 5.8 a buck2 2.8 4 5.2 buck3 2.6 3.7 4.8 buck4 2.8 4.1 5.3 under-voltage protection uvp voutb1s to voutb4s < 0.66 x (v out target) 56 66 76 % maximum output current i max buck1 2.4 -- -- a buck2 2 -- -- buck3 1.6 -- -- buck4 2.0 -- -- output transient response v peak 0.8a to 1.6a at 20 ? s, v out = 1.2v buck1 and buck2 ? 4 -- 4 % high-side on-resistance r pon v in = 3.7v 50 150 250 m ? low-side on-resistance r non v in = 3.7v 40 110 160 m ?
8 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit ldo1 to ldo8 input voltage for vinl123/456/78 v inl 2.5 -- 5.5 v output voltage ldo123/78 v outl 3.1v ? v in ? 5.5v, 50 ? a ? i out ? i max ? 3% 1.6 to 3.6 3% v output voltage ldo456 v outl 3.1v ? v in ? 5.5v, 50 ? a ? i out ? i max ? 3% 3 to 3.6 3% v output current i out 300 -- -- ma output short current isht 330 450 600 ma voltage difference v in ? v out v in > 3.1v v in = v set , i out = i outmax 0.05 0.1 0.3 v v in > 2.5v 0.05 0.11 0.5 output voltage temperature coefficient -- 100 -- ppm/ ? c supply current i ss i out = 0ma 10 35 60 ? a shutdown current i off 0 1 2 ? a line regulation input 3v to 5v, load = 100ma 0 1 5 mv load regulation v in = 5v, load 100ma to 300ma 0 0.1 1 % transient response ? v out 50 ? a ? i outmax / 2 ( S t = 1 ? s) -- 50 -- mv ripple rejection f = 10khz, i out = i outmax / 2 -- 60 -- db rising time v out ? 0.7 x v tar g et , i out = 0ma 150 220 300 ? s falling time v out ? 0.3 x v tar g et , i out = 0ma 300 600 1000 ? s i 2 c interface electrical characteristics voltage output low v ol -- -- 0.4 v input voltage high-lev el v ih 1.5 -- -- v low-level v il -- -- 0.4 scl clock scl -- -- 400 khz note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
9 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit RT5028C enl1 to enl8 enb1 to enb4 vinl456 vinl123 2 7 agnd 21, 34, 56, 57 (exposed pad) vinl78 10 voutl3 voutl4 voutl5 voutl6 voutl8 voutl7 1f 1f voutl2 voutl1 1f 1f 1f 1f 1 3 4 8 6 5 9 11 1f 1f 1f 1f 1f vddp 51 1f vin 52 1f vinb2 lxb2 voutb2s 22f 2.2h 10f 43, 44 41, 42 39 vinb1 lxb1 voutb1s 22f 2.2h 10f 45, 46 47, 48 50 vinb4 lxb4 voutb4s 22f 2.2h 10f 32 31 29 vinb3 lxb3 voutb3s 22f 2.2h 10f 37, 38 35, 36 33 pwron 22 irq scl sda 15 16 19 reboot pwrhold 20 26 reset saddr mtp mask_gpio ap 23 24 25 27 as saddr connect to agnd slave address =0111111 as saddr connect to vin slave address =0110111 as mask_gpio connect to agnd en pins can control. as mask_gpio connect to vin ignore all en pins. as mtp connect to agnd inhibit to write mtp. as mtp connect to vin permit to write mtp. saddr mask_gpiomtp agnd vin
10 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics ch1 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency (%) v out = 1.35v, l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v ch2 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency (%) v out = 1.5v, l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v ch3 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency (%) v out = 1.2v, l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v ch4 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency (%) v out = 3.3v, l = 2.2 h, c out = 10 f v in = 3.6v v in = 3.9v v in = 4.2v v in = 4.5v v in = 5v v in = 5.5v ch2 buck output voltage vs. output current 1.47 1.48 1.49 1.50 1.51 1.52 1.53 0 500 1000 1500 2000 output current (a) output voltage (v) l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v ch1 buck output voltage vs. output current 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 0 300 600 900 1200 1500 1800 2100 2400 output current (ma) output voltage (v) l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v
11 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ch4 buck output voltage vs. input voltage 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) output voltage (v) l = 2.2 h, c out = 10 f i out = 0ma i out = 500ma i out = 1000ma i out = 1500ma i out = 2000ma ch3 buck output voltage vs. input voltage 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) output voltage (v) l = 2.2 h, c out = 10 f i out = 0ma i out = 500ma i out = 1000ma i out = 1600ma ch1 buck output voltage vs. input voltage 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) output voltage (v) l = 2.2 h, c out = 10 f i out = 0ma i out = 500ma i out = 1000ma i out = 1500ma i out = 2000ma i out = 2400ma ch2 buck output voltage vs. input voltage 1.45 1.47 1.49 1.51 1.53 1.55 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) output voltage (v) l = 2.2 h, c out = 10 f i out = 0ma i out = 500ma i out = 1000ma i out = 1500ma i out = 2000ma ch4 buck output voltage vs. output current 3.08 3.13 3.18 3.23 3.28 3.33 3.38 0 500 1000 1500 2000 output current (ma) output voltage (v) l = 2.2 h, c out = 10 f v in = 3.6v v in = 3.9v v in = 4.2v v in = 4.5v v in = 5v v in = 5.5v ch3 buck output voltage vs. output current 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 0 200 400 600 800 1000 1200 1400 1600 output current (ma) output voltage (v) l = 2.2 h, c out = 10 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v
12 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ldo7 output voltage vs. input voltage 2.40 2.42 2.44 2.46 2.48 2.50 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) i out = 0ma i out = 100ma i out = 200ma i out = 300ma c out = 1 f ldo5 output voltage v s. input voltage 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.3 3.8 4.3 4.8 5.3 5.8 input voltage (v) output voltage (v) i out = 0ma i out = 100ma i out = 200ma i out = 300ma c out = 1 f ldo7 output voltage vs. output current 2.40 2.42 2.44 2.46 2.48 2.50 2.52 0 50 100 150 200 250 300 output current (ma) output voltage (v) c out = 1 f v in = 2.5v v in = 3v v in = 3.6v v in = 4.2v v in = 5v v in = 5.5v ldo2 output voltage vs. input voltage 1.75 1.76 1.76 1.77 1.77 1.78 1.78 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) i out = 0ma i out = 100ma i out = 200ma i out = 300ma c out = 1 f ldo2 output voltage vs. output current 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 0 50 100 150 200 250 300 output current (ma) output voltage (v) c out = 1 f v in = 2.5v v in = 3v v in = 3.6v v in = 4.2v v in = 5v v in = 5.5v ldo5 output voltage vs. output current 3.20 3.22 3.24 3.26 3.28 3.30 3.32 0 50 100 150 200 250 300 output current (ma) output voltage (v) c out = 1 f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 5v v in = 5.5v
13 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. read function reading one indexed byte of data from rt (with 1-byte) application information the RT5028C is a highly-integrated solution for industrial system including pmic and memory system. the RT5028C application mechanism and i 2 c compatible interface are introduced in later sections. the system's slave address is 0110111 (as saddr = high) or 0111111(as saddr = low). pmic - power management system provides 8 low dropout linear regulator and 4 high efficiency synchronous step- down dc/dc converters. power-on and power-off sequences are control by pwron and reset input pins. s slave address 0 a register address a data byte a p r/w acknowledge from rt acknowledge from rt acknowledge from master sr slave address 1 a acknowledge from rt repeated start r/w 1byte reading n indexed words of data from rt (with n-byte) s slave address 0 a register address a data byte a data byte a p acknowledge from rt acknowledge from rt acknowledge from master acknowledge from master sr slave address 1 a acknowledge from rt repeated start data byte a data byte a acknowledge from master acknowledge from master r/w r/w 1st byte 2nd byte (n-1)th byte nth byte detail time sequence control is described in power on/ off diagram. the i 2 c interface can program individual regulator output voltage as well as on/off control and voltage setting. i 2 c interface timing diagram the RT5028C acts as an i 2 c -bus slave. the i 2 c-bus master configures the settings for all function blocks by sending command bytes to the RT5028C via the 2-wire i 2 c-bus. the i 2 c timing diagrams are list in the following. write function writing one byte of data to rt (with 1-byte) s slave address 0 a register address a data byte a p r/w acknowledge from rt acknowledge from rt acknowledge from rt 1byte writing n bytes of data to rt (with n-byte) s slave address 0 a register address a data byte a data byte a p acknowledge from rt acknowledge from rt acknowledge from rt acknowledge from rt a acknowledge from rt r/w (n-1)th byte nth byte data byte 1st byte a acknowledge from rt data byte 2nd byte
14 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pmic power channels control methodology when vin power good or pwron event occurs, the pmic will follow the power on sequence to turn on channels. during normal operation, users can use the reboot pin to restart pmic again. another pwroff event, otp or uvp occurs, pmic will execute the power off. in the RT5028C pmic, the uvp event will be set out when the buck1 to buck4s' output voltage is lower than 1/2 x (v out ). power off pwron check power on sequence normal operation otp check uvp check pwroff check reboot check power off no yes no yes yes yes yes no no no vin power good yes no edge trigger edge trigger mask_gpio 1 (internal i 2 c) external en check yes no reboot check yes 0 (external enable control)
15 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pmic - power on/off setting the circuit setting for communication between RT5028C and ap is showed as below. power hold function when the ? pwrhold ? signal does not come during thold time, the RT5028C will do shutdown sequence. if users want to disable power hold function, set ? disthold ? bit in i 2 c register 10 bit[0] to disable this function. in the timing diagram below, the ? thold ? and ? reset_dly ? can be set by mtp program. buck1 ldo1 ldo8 pwron buck4 pwrhold thold always low start_time turn off sequence : first-on-last-off reset reset_dly state machine enl1 to enl8 enb1 to enb4 pwron irq scl sda reboot pwrhold saddr mtp mask_gpio ap reset saddr mask_gpiomtp agnd vin as saddr connect ot agnd slave address =0111111 as saddr connect ot vin slave address =0110111 as mask_gpio connect ot agnd en pins can control. as mask_gpio connect ot vin ignore all en pins. as mtp connect ot agnd inhibit to write mtp. as mtp connect ot vin permit to write mtp.
16 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. when ap sends the ? pwrhold ? signal during thold time, the RT5028C will keep power-on. buck1 ldo1 ldo8 buck4 pwrhold pwron thold low to high signal from ap. start_time reset reset_dly timing based on/off sequence buck1 buck2 ldo1 ldo8 pwron buck4 start_time normal power on ... normal power off shdn_press tss tss tss tss reset reset_dly
17 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. level based on/off sequence buck1 buck2 ldo1 ldo8 pwron buck4 start_time normal power on >80 % normal power off 8ms >80 % >80 % >80 % shdn_press 8ms reset_dly reset abnormal off buck1 buck2 ldo1 ldo8 irq pwron buck4 start_time shdn_dlytime tss tss normal power on abnormal power off irq even occur reset_dly reset
18 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pmu on/off sequence setting in the RT5028C, users can set the power on/off sequence and output voltage by i 2 c register 0x01 to 0x04 for buck output voltage, 0x07 to 0x0e for ldo output voltage and 0x2c to 0x32 for startup sequence setting. in the table below, users must set one by one (continues number) and missing code is not allowed. if users miss sequence code, the RT5028C will wait for next channel and the ic will be hold in waiting status. output voltage setting startup sequence setting startup enable method (soft-start control) buck1output[5:0] buck1_seq[3:0] buck1 [000000] [0001] buck2output[5:0] buck2_seq[3:0] buck2 [101100] [0010] buck3output[5:0] buck3_seq[3:0] buck3 [000000] [0011] buck4output[5:0] buck4_seq[3:0] buck4 [101100] [0100] ldo1out[6:0] ldo1_seq[3:0] ldo1 [0000000] [0101] ldo2out[6:0] ldo2_seq[3:0] ldo2 [0101000] [0110] ldo3out[6:0] ldo3_seq[3:0] ldo3 [0000000] [0111] ldo4out[6:0] ldo4_seq[3:0] ldo4 [0101000] [1000] ldo5out[6:0] ldo5_seq[3:0] ldo5 [0000000] [1001] ldo6out[6:0] ldo6_seq[3:0] ldo6 [0101000] [1010] ldo7out[6:0] ldo7_seq[3:0] ldo7 [0000000] [1011] ldo8out[6:0] ldo8_seq[3:0] ldo8 [0101000] [1100] [10] note : * output voltage setting: fill relative binary code to set the output voltage. * startup sequence setting : ? 0000 ? denotes no operation (disable). ? 0001 ? denotes first-startup. ? 1100 to 1111 ? denotes last-startup. if same number, it means startup at the same time. *startup enable method : [01] to [11] : each startup enable interval time (1ms, 4ms, 8ms). [00] : start end voltage (the output voltage's 80%)
19 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. synchronous step-down dc/dc converter four current mode synchronous step-down dc/dc converters operate with internal power mosfets and compensation network. these channels supply the power core chip of portable system. they can be operated at 100% maximum duty cycle to extend battery operating voltage range. when the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. the operating frequency range of step-down converter is 0.5mhz to 2mhz. four step-down converters have ramp control function as the following diagram. dc/dc 1/2/3/4 output voltage1 dc/dc 1/2/3/4 output voltage2 dc/dc 1/2/3/4 output voltage3 dc/dc 1/2/3/4 output voltage4 reboot function as the reboot pin is set from low to high, the reboot function will be active. the reboot's fsm is shown as below. it concludes 100ms de-bouncing time and delay1/ delay2 power off delay time. table 1. reboot input control setting description default delayed2 10 delayed1 00 : 100ms 10 : 1s 01 : 500ms 11 : 2s 10 action delayed1 power-off then delayed2 power-on pmic irq_enable_ovp ovp irq_status_ovp irq_pmic mask irq_status reset after read reset after read from ?low? to ?high? rising input into reboot pin with 100ms debouncing time wait for delayed1 time power off the pmic wait for delayed2 time power on the pmic irq table we summarize all irq items in the register table. all irq_status registers are implemented as reset after read. if irq_enable bit is low, the irq_status bit will not update status. irq_enable will mask irq_status to trigger irq_pmic low, so the system can decide which interrupt is necessary. waveform - (when the other irq_status are low) waveform - (when the other irq_status are low) * otw125/otw100 means the 125 c /100 c pre-warming over temperature. it only change irq status bits and don't trigger irq pin.
20 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. eeprom (mtp) control flow the RT5028C embeds 32 bytes mtp memory, and it allows users to save some i 2 c register bank data to mtp. when the i 2 c register 0x3a bit[0]/bit[1] is wrote to ? 1 ? , the mtp page1/page2 will execute erase process firstly. because the erase process will be done in every writing time, the mtp data will be missed. so it would be best for users to read data from mtp to i 2 c first before executing writing process. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-56l 7x7 package, the thermal resistance, ja , is 27 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (27 c/w) = 3.7w for wqfn-56l 7x7 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 1. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb set i 2 c register 0x3a bit[4] =1 pmu will read mtp data to relative i 2 c register bank. set i 2 c register 0x3a bit[0] pmu will erase the mtp page1 data pmu will move relative i 2 c register bank data to mtp reading mtp process writing mtp process page 1 writing follow : set i 2 c register 0x3a bit[5] =1 pmu will read mtp data to relative i 2 c register bank. set i 2 c register 0x3a bit[1] pmu will erase the mtp page2 data pmu will move relative i 2 c register bank data to mtp reading mtp process writing mtp process page 2 writing follow :
21 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout consideration for the best performance of the RT5028C, the following pcb layout guidelines must be strictly followed. ? place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. ? keep the main power traces as wide and short as possible. ? the switching node area connected to lx and inductor should be minimized for lower emi. ? connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. ? directly connect the output capacitors to the feedback network of each channel to avoid bouncing caused by parasitic resistance and inductance from the pcb trace. figure 2. pcb layout guide 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 53 54 55 56 voutl1 vinl123 voutl2 voutl3 voutl6 vinl456 voutl4 voutl7 vinl78 scl sda enl7 enl8 irq /reset mask_gpio lxb2 lxb2 enb2 vinb3 lxb3 lxb3 agnd voutb3s agnd enl3 enl1 vin vddp voutb1s agnd pwron reboot enb1 lxb1 lxb1 enl2 gnd gnd gnd connect the exposed pad to a ground plane. input/output capacitors must be placed as close as possible to the input/output pins. gnd voutb2s vin voutb2 gnd 10 14 13 12 11 25 26 27 28 29 30 31 32 vinb4 lxb4 enb3 voutb4s 43 44 45 46 vinb1 vinb2 voutl8 enl4 enl5 enl6 mtp pwrhold saddr enb4 vinb3 vinb2 vinb1 vin gnd gnd gnd gnd voutl5 vin voutb1 voutb3 gnd gnd voutb4 gnd vin vin vin vin vin lx should be connected to inductor by wide and short trace, keep sensitive compont ents away from this trace.
22 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. i 2 c register table detail description address 00 device id bit name description read/write reset value [7:4] vendor_id vendor identification : richtek : 1000b r 1000 [3:0] chip_rev chip revision r 0001 address 01 buckcontrol1 bit nam e description r/w reset value [7:2] buck1output[5:0] buck1 output voltage regulation 000000 : 0.7v, 25mv per step 000001 : 0.725v ? 101100 : 1.8v ? 111111 : 1.8v r/w option [1:0] buck1vrc vrc setting 00 : 50mv/10 ? s, 01 : 50mv/10 ? s, 10 : 100mv/10 ? s, 11 : 200mv/10 ? s r/w option address 02 buckcontrol2 bit name description r/w reset value [7:2] buck2output[5:0] buck2 output voltage regulation 000000 : 0.7v, 25mv per step 000001 : 0.725v ? 101100 : 1.8v ? 111111 : 1.8v r/w option [1:0] buck2vrc vrc setting 00 : 50mv/10 ? s, 01 : 50mv/10 ? s, 10 : 100mv/10 ? s, 11 : 200mv/10 ? s r/w option address 03 buckcontrol3 bit nam e description r/w reset value [7:2] buck3output[5:0] buck3 output voltage regulation 000000 : 0.7v, 50mv per step 000001 : 0.75v ? 111010 : 3.6v ? 111111 : 3.6v r/w option [1:0] buck3vrc vrc setting 00 : 50mv/10 ? s, 01 : 100mv/10 ? s, 10 : 200mv/10 ? s, 11 : 400mv/10 ? s r/w option
23 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 04 buckcontrol4 bit name description r/w reset value [7:2] buck4output[5:0] buck4 output voltage regulation 000000 : 0.7v, 50mv per step 000001 : 0.75v ? 111010 : 3.6v ? 111111 : 3.6v r/w option [1:0] buck4vrc vrc setting 00 : 50mv/10 ? s, 01 : 100mv/10 ? s, 10 : 200mv/10 ? s, 11 : 400mv/10 ? s r/w option address 05 vrc control bit name description r/w reset value 7 buck1vrc_en buck1 vrc 0 : disable - voltage ramps up to target voltage with one time 1 : enable - voltage ramps up to target voltage with slope control r/w option 6 buck2vrc_en buck2 vrc 0 - disable - voltage ramps up to target voltage with one time 1 - enable - voltage ramps up to target voltage with slope control r/w option 5 buck3vrc_en buck3 vrc 0 : disable - voltage ramps up to target voltage with one time 1 : enable - voltage ramps up to target voltage with slope control r/w option 4 buck4vrc_en buck4 vrc 0 : disable - voltage ramps up to target voltage with one time 1 : enable - voltage ramps up to target voltage with slope control r/w option [3:0] reserved r/w 0000 address 06 buck mode bit name description r/w reset value 7 buck1mode buck1 mode 0 : force pwm 1 : auto mode (psm/pwm) r/w 1 6 buck2mode buck2 mode 0 : force pwm 1 : auto mode (psm/pwm) r/w 1 5 buck3mode buck3 mode 0 : force pwm 1 : auto mode (psm/pwm) r/w 1
24 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. 4 buck4mode buck4 mode 0 : force pwm 1 : auto mode (psm/pwm) r/w 1 3 buck1oms buck1 output off mode state 0 : floating 1 : ground-discharged r/w 1 2 buck2oms buck2 output off mode state 0 : floating 1 : ground-discharged r/w 1 1 buck3oms buck3 output off mode state 0 : floating 1 : ground-discharged r/w 1 0 buck4oms buck4 output off mode state 0 : floating 1 : ground-discharged r/w 1 address 07 ldocontrol1 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo1out[6:0] ldo1 output voltage regulation 0000000 : 1.6v, 25mv per step 0000001 : 1.625v ... 0101000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 08 ldocontrol2 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo2out[6:0] ldo2 output voltage regulation 0000000 : 1.6v, 25mv per step 0000001 : 1.625v ... 0101000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 09 ldocontrol3 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo3out[6:0] ldo3 output voltage regulation 0000000 : 1.6v, 25mv per step 0000001 : 1.625v ... 0101000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option
25 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 0a ldocontrol4 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo4out[6:0] ldo4 output voltage regulation 0000000 : 3 v, 25mv per step 0000001 : 3.025v ... 0011000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 0b ldocontrol5 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo5out[6:0] ldo5 output voltage regulation 0000000 : 3v, 25mv per step 0000001 : 3.025v ... 0011000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 0c ldocontrol6 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo6out[6:0] ldo6 output voltage regulation 0000000 : 3.0v, 25mv per step 0000001 : 3.025v ... 0011000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 0d ldocontrol7 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo7ut[6:0] ldo7output voltage regulation 0000000 : 1.6v, 25mv per step 0000001 : 1.625v ... 0101000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option
26 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 0e ldocontrol8 bit name description r/w reset value 7 reserved r/w 0 [6:0] ldo8t[6:0] ldo8utput voltage regulation 0000000 : 1.6v, 25mv per step 0000001 : 1.625v ... 0101000 : 3.6v (max) ? 1111111 : 3.6v (max) r/w option address 0f ldos off mode state bit name description r/w reset value 7 ldo8oms ldo8 output off mode state 0 : floating 1 : ground-discharged r/w 1 6 ldo7oms ldo7 output off mode state 0 : floating 1 : ground-discharged r/w 1 5 ldo6oms ldo6 output off mode state 0 : floating 1 : ground-discharged r/w 1 4 ldo5oms ldo5 output off mode state 0 : floating 1 : ground-discharged r/w 1 3 ldo4oms ldo4 output off mode state 0 : floating 1 : ground-discharged r/w 1 2 ldo3oms ldo3 output off mode state 0 : floating 1 : ground-discharged r/w 1 1 ldo2oms ldo2 output off mode state 0 : floating 1 : ground-discharged r/w 1 0 ldo1ms ldo1output off mode state 0 : floating 1 : ground-discharged r/w 1 address 10 reboot/pwrhold delay time control bit name description r/w reset value [7:6] delayed2[1:0] delayed2 setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) r/w option [5:4] delayed1[1:0] delayed1 setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) r/w option [3:2] thold[1:0] thold setting (00 : 100ms/01 : 500ms/10 : 1s/11 : 2s) r/w option 1 reserved r/w 0 0 disthold ignore thold time. 0 : keep pwrhold function. 1 : ignore pwrhold function. r/w option
27 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 11 on event setting bit name description r/w reset value [7:5] on_event powered on because of 000 : pwron key-pressed 001 : vin plugged in 010 : from reboot pin event 111 : no event happen r 111 [4:0] reserved r/w 0 address 12 vin uvlo/buck on/off bit name description r/w reset value [7:5] voff setting vin uvlo 2.8v to 3.5v per 0.1v to power off pmic 000 : 2.8v 001 : 2.9v 010 : 3v 011 : 3.1v (default) 100 : 3.2v 101 : 3.3v 110 : 3.4v 111 : 3.5v r/w option 4 reserved r/w 0 3 buck4 buck4 control (0 : disable buck4/1 : enable buck4) r/w option 2 buck3 buck3 control (0 : disable buck3/1 : enable buck3) r/w option 1 buck2 buck2 control (0 : disable buck2/1 : enable buck2) r/w option 0 buck1 buck1 control (0 : disable buck1/1 : enable buck1) r/w option address 13 ldos on/off bit name description r/w reset value 7 ldo8 ldo8 control (0 : disable ldo8 / 1 : enable ldo8) r/w option 6 ldo7 ldo7 control (0 : disable ldo7 / 1 : enable ldo7) r/w option 5 ldo6 ldo6 control (0 : disable ldo6 / 1 : enable ldo6) r/w option 4 ldo5 ldo5 control (0 : disable ldo5 / 1 : enable ldo5) r/w option 3 ldo4 ldo4 control (0 : disable ldo4 / 1 : enable ldo4) r/w option 2 ldo3 ldo3 control (0 : disable ldo3 / 1 : enable ldo3) r/w option 1 ldo2 ldo2 control (0 : disable ldo2 / 1 : enable ldo2) r/w option 0 ldo1 ldo1 control (0 : disable ldo1 / 1 : enable ldo1) r/w option
28 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 14 pwron(power on key) time parameters setting / reset delay bit name description r/w reset value [7:6] start_time startup time setting 00 : 100us (pressing time - low level) 01 : 100ms 10 : 1s 11 : 2s r/w option [5:4] l_press_time long-press time setting (after power-on, 00 : 1s (falling edge to rising edge) 01 : 1.5s 10 : 2s 11 : 2.5s sending short/long-press irq to cpu ex :1.5s => low time < 1.5s (short irq) => low time > 1.5s but < 6s(shutdown time) (long irq) => low time > 6s(shutdown time) (shutdown) r/w option [3:2] shdn_press key-press forced shutdown time setting 00 : 4s (pressing time : low level) 01 : 6s 10 : 8s 11 : 10s r/w option [1:0] reset_dly reset signal delay after the last power startup is done 00 : 10ms 01 : 50ms 10 : 100ms 11 : 200ms r/w option address 15 shdn control bit name description read/write reset value 7 shdn_ctrl power off setting by cpu, after set, 100ms delayed power off 0 : normal operation 1 : disable the pmic output r/w option 6 shdn_timing disable buck/ldo only for normal power off (shdn_ctrl=1) 0 : disable at the same time 1 : contrary to the startup timing (first_on-last_off) r/w option [5:4] shdn_dlytime delayed shutdown time after send the (pwron)key-press-forced-shutdown irq (when irq is disable, there is no delay) 00 : 100ms 01 : 500ms 10 : 1s 11 : 2s r/w option [3:0] reserved r/w 0000
29 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 16 powered off conditions enable setting bit name description read/write reset value 7 bck1lv_enshdn buck1 output voltage low shdn 0 : disable this event. 1 : enable this event r/w 0 6 bck2lv_enshdn buck2 output voltage low shdn 0 : disable this event. 1 : enable this event r/w 0 5 bck3lv_enshdn buck3 output voltage low shdn 0 : disable this event. 1 : enable this event r/w 0 4 bck4lv_enshdn buck4 output voltage low shdn 0 : disable this event. 1 : enable this event r/w 0 3 pwron_enshdn pwron key-pressed forced shdn 0 : disable this event. 1 : enable this event r/w 1 2 ot_enshdn over temperature shdn 0 : disable this event. 1 : enable this event r/w 1 1 vinlv_enshdn vin voltage low (voff) (set by reg) shdn 0 : disable this event. 1 : enable this event r/w 0 0 reserved r/w 0 address 17 off event (only reset by por) bit name description read/write reset value [7:4] off_event powered off because of (only shows last power-off event) 0000 : vin voltage low (voff) (set by reg) 0001 : buck1 output voltage low 0010 : buck2 output voltage low 0011 : buck3 output voltage low 0100 : pwron key-pressed forced shutdown 0101 : power off register setting 0110 : over temperature event 0111 : reboot restart. 1000 : buck4 output voltage low 1001 : pwr_hold fail. 1010 : no event happen. ?. 1111 : no event happen r 1111 [3:0] reserved r 0000 address 18 to 27 16 bytes registers data cache (only reset by por) r/w 0
30 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. irq_pmic (power channels) address 28 irq enable1 bit name description read/write reset value 7 ot_irq internal over-temperature was triggered, irq enable r/w 1 6 bck1lv_irq buck1 output voltage equal 66% x v ta r g e t , irq enable r/w 1 5 bck2lv_irq buck2 output voltage equal 66% x v ta r g e t , irq enable r/w 1 4 bck3lv_irq buck3 output voltage equal 66% x v ta r g e t , irq enable r/w 1 3 bck4lv_irq buck4 output voltage equal 66% x v ta r g e t , irq enable r/w 1 2 pwronsp_irq pwron short press, irq enable (32 ? s deglitch time) r/w 0 1 pwronlp_irq pwron long press, irq enable (32 ? s deglitch time) r/w 0 0 syslv_irq vin voltage is lower than voff, irq enable r/w 0 address 29 irq status1 bit name description read/write reset value 7 ot internal over-temperature r 0 6 bck1lv buck1 output voltage equal 66% x v ta r g e t r 0 5 bck2lv buck2 output voltage equal 66% x v ta r g e t r 0 4 bck3lv buck3 output voltage equal 66% x v ta r g e t r 0 3 bck4lv buck4 output voltage equal 66% x v ta r g e t r 0 2 pwronsp pwron short press (32 ? s deglitch time) r 0 1 pwronlp pwron long press (32 ? s deglitch time) r 0 0 vinlv vin voltage is lower than voff r 0 address 2a irq enable2 bit name description read/write reset value 7 kpshdn_irq key-press forced shutdown, irq enable r/w 1 6 pwronr_irq pwron press rising edge, irq enable r/w 0 5 pwronf_irq pwron press falling edge, irq enable r/w 0 [4:0] reserved r 0000 address 2b irq status2 bit name description read/write reset value 7 kpshdn key-press forced shutdown r 0 6 pwronr pwron press rising edge r 0 5 pwronf pwron press falling edge r 0 [4:2] reserved r 000 1 otw125 internal 125 ? c pre-warning over-temperature. r 0 0 otw100 internal 100 ? c pre-warning over-temperature. r 0
31 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. address 2c pmu on/off sequence1 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] buck2_seq[3:0] setting buck2 on/off sequence priority r/w option [3:0] buck1_seq[3:0] setting buck1 on/off sequence priority r/w option address 2d pmu on/off sequence2 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] buck4_seq[3:0] setting buck4 on/off sequence priority r/w option [3:0] buck3_seq[3:0] setting buck3 on/off sequence priority r/w option address 2e pmu on/off sequence3 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] ldo2_seq[3:0] setting ldo2 on/off sequence priority r/w option [3:0] ldo1_seq[3:0] setting ldo1 on/off sequence priority r/w option address 2f pmu on/off sequence4 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] ldo4_seq[3:0] setting ldo4 on/off sequence priority r/w option [3:0] ldo3_seq[3:0] setting ldo3 on/off sequence priority r/w option address 30 pmu on/off sequence5 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] ldo6_seq[3:0] setting ldo6 on/off sequence priority r/w option [3:0] ldo5_seq[3:0] setting ldo5 on/off sequence priority r/w option address 31 pmu on/off sequence5 bit name description (setting on/off sequence priority) (0000 : off, 0001 : first on, 1100 : last on) (the sequence is planed by first on last off) read/write reset value [7:4] ldo8_seq[3:0] setting ldo8 on/off sequence priority r/w option [3:0] ldo7_seq[3:0] setting ldo7 on/off sequence priority r/w option address 32 soft-start control bit name description read/write reset value [7:6] reserved r option
32 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. [5:2] soft-start end control @ mask_gpio = 0 (external enable pin define) 0000 : first turn on channel decide the reset_dly time. 0001 : buck1 decide the reset_dly time. ?. 0100 : buck1 decide the reset_dly time. 0101 : ldo1 decide the reset_dly time. ?. 1100 : ldo8 decide the reset_dly time. ?. 1111 : ldo8 decide the reset_dly time. r/w option [1:0] soft-start voltage level / time soft-start control. voltage level 00 : when output voltage arrives to 80% v tar g et , next channel will turn on. soft-start time interval (tss) : 01 : 1ms 10 : 4ms 11 : 8ms r/w option address 33 buck syn-clock control bit name description read/write reset value [7:6] vco_vrc vco input voltage slop. 00: 25mv/10 ? s, 01: 25mv/20 ? s 10: 25mv/40 ? s, 11: 25mv/80 ? s note : the vco?s voltage input range is 0.375v to 1.8v and the output frequency is 450khz to 2mhz. r/w option [5:0] vco_dvs vco input voltage dvs control 000000 : 0.375v (450khz) ??? 111001 : 1.8v (2mhz) ??? 111111 : 1.8v (2mhz) r/w option address 34 buck syn-clock spread spectrum control bit name description read/write reset value [7:1] reserved r/w 0000000 0 ssosc buck clock spread spectrum control 0 : disable spread spectrum function. 1 : turn on spread spectrum function. r/w option address 3a eeprom (mtp) control bit name description read/write reset value [7:6] reserved r/w 00 5 mtp page 2 read read mtp page 2 r 0 4 mtp page 1 read read mtp page 1 r 0 [3:2] reserved r/w 00 1 mtp page 2 write write mtp page 2, and mtp also needs to be logic high. w 0 0 mtp page 1 write write mtp page 1, and mtp also needs to be logic high. w 0
33 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 3. i 2 c to mtp mapping table mtp page-1 mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 0x01 function buckcontrol1 meaning buck1output[5:0] buck1vrc default 0 1 0 1 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a b b 0x01 0x02 function buckcontrol2 meaning buck2output[5:0] buck2vrc default 0 1 1 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a b b 0x02 0x03 function buckcontrol3 meaning buck3output[5:0] buck3vrc default 0 1 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a b b 0x03 0x04 function buckcontrol4 meaning buck4output[5:0] buck4vrc default 1 1 0 1 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a b b 0x0d 0x05 function vrc control meaning buck1v rc_en buck2v rc_en buck3v rc_en buck4v rc_en reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b 0x04 0x07 function ldocontrol1 meaning reserved ldo1out[6:0] default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a
34 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 0x08 function ldocontrol2 meaning reserved ldo2out[6:0] default 0 0 1 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x06 0x09 function ldocontrol3 meaning reserved ldo3out[6:0] default 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x07 0x0a function ldocontrol4 meaning reserved ldo4out[6:0] default 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x08 0x0b function ldocontrol5 meaning reserved ldo5out[6:0] default 0 0 0 1 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x09 0x0c function ldocontrol6 meaning reserved ldo6out[6:0] default 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x0a 0x0d function ldocontrol7 meaning reserved ldo7out[6:0] default 0 1 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a 0x0b 0x0e function ldocontrol8 meaning reserved ldo8out[6:0] default 0 0 0 0 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b a a a a a a a
35 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0c 0x12 function vin uvlo (update default value after power on) meaning voff setting reserved reserved reserved reserved reserved default 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a b b b b b 0x0f no mapping function x meaning reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b
36 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mtp page-2 mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 0x10 function reboot/pwrhold delay time control meaning delayed2[1:0] delayed1[1:0] thold reserved disthold default 1 0 1 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b 0x01 0x14 function pwron time parameters setting / reset delay meaning start_time l_press_time shdn_press reset_dly default 0 0 0 0 0 0 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x02 0x15 function shdn control meaning shdn_ ctrl shdn_ timing shdn_dlytime reserved reserved reserved reserved default 0 1 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b 0x03 0x2c function pmu on/off sequence1 meaning buck2_seq[3:0] buck1_seq[3:0] default 0 0 0 1 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x04 0x2d function pmu on/off sequence2 meaning buck4_seq[3:0] buck3_seq[3:0] default 0 0 1 0 0 0 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x05 0x2e function pmu on/off sequence3 meaning ldo2_seq[3:0] ldo1_seq[3:0] default 0 0 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a
37 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x06 0x2f function pmu on/off sequence4 meaning ldo4_seq[3:0] ldo3_seq[3:0] default 0 0 0 0 0 0 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x07 0x30 function pmu on/off sequence5 meaning ldo6_seq[3:0] ldo5_seq[3:0] default 0 0 1 1 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x08 0x31 function pmu on/off sequence6 meaning ldo8_seq[3:0] ldo7_seq[3:0] default 0 0 1 1 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a 0x09 0x32 function soft-start control meaning reversed reversed soft-start end select @mask_gpio=1 soft-start control default 0 0 0 1 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b a a a a b b 0x0a 0x33 function buck syn-clock control meaning vco_vrc vco_dvs default 0 0 1 1 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b a a a a a a 0x0b 0x34 function buck syn-clock spread spectrum control meaning reversed reversed reversed reversed reversed reversed reversed ssosc default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b 0x0c no mapping function x meaning reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b
38 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mtp address i 2 c register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fun ction x meaning reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 0x0d no map ping rese t condition b b b b b b b b fun ction x meaning reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 0x0e no map ping rese t condition b b b b b b b b fun ction x meaning reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 0x0f no map ping rese t condition b b b b b b b b reset condition a reset by mtp (register 0x12 voff setting). b reset when vin <1.7v.
39 ds5028c-00 march 2015 www.richtek.com RT5028C ? copyright 2015 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 6.900 7.100 0.272 0.280 d2 5.150 5.250 0.203 0.207 e 6.900 7.100 0.272 0.280 e2 5.150 5.250 0.203 0.207 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 56l qfn 7x7 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
40 ds5028c-00 march 2015 www.richtek.com RT5028C richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries.

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